Sequential logic such as flip-flops or data latches may output and hold a value corresponding to a data input signal. This may be in response to an operable clock edge. In order for a value to be output correctly, a data input signal should adhere to a certain conditions, for example, set-up and hold time for the latch. The set-up time is the period of time prior to the operable clock edge that the data input signal should hold its value in order to be clocked out correctly. The hold time is the period of time after an operable clock edge the data signal input should hold its value in order to be clocked out correctly.
Sequential logic, for example, data latches, may be implemented in systems where dynamic scaling is used. In such systems, a system voltage and/or frequency may be adjusted until the system is close to failure in order to attain a performance payoff, for example power savings. In such systems, a frequency and or voltage, directly or indirectly provided to the latch, may be adjusted such that the set-up and hold times of a data input signal are as close as possible to minimum set-up and hold times of a latch.
In some systems, the sequential logic may be monitored to detect a failure. In some systems, this monitoring may be implemented as a shadow latch in conjunction with the sequential logic clocking the data through. The shadow latch may be made closer to failure than the sequential logic under similar conditions. For example, minimum set-up and hold times of the shadow latch may be longer than the minimum set-up and hold times of the sequential logic. The shadow latch may indicate that it has failed, and the system may stop scaling the voltage and or frequency to prevent the failure of the sequential logic.
In these systems, the minimum set-up and hold times of the shadow latch may be set according to a limit as to how close to failure the sequential logic may be driven. Additionally, such shadow latches consume power and take up space.